| PART |
Description |
Maker |
| MC10EP29MNTXG |
3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 10E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC20
|
ON Semiconductor
|
| MC100LVEL29DWR2 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20
|
ON Semiconductor
|
| IN74LV74 IN74LV74D |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
Integral Corp.
|
| 74ALVC74PW 74ALVC74 74ALVC74BQ 74ALVC74D |
Dual D-type flip-flop with set and reset; positive-edge trigger
|
PHILIPS[Philips Semiconductors]
|
| 74LVC74ABQ |
74LVC74A; Dual D-type flip-flop with set and reset; positive-edge trigger
|
Philips
|
| 74HC74 74HC74PW 74HCT74PW 74HC74BQ 74HC74D 74HC74N |
74HC74; 74HCT74; Dual D-type flip-flop with set and reset; positive-edge trigger
|
PHILIPS[Philips Semiconductors]
|
| 74F50729 N74F50729N I74F50729D I74F50729N N74F5072 |
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| HCTS74MS |
Flip Flop, D-Type, with Set and Reset, TTL Inputs, Dual, Rad-Hard, High-Speed, CMOS, Logic
|
Intersil
|
| 74AUP1G74GT-G 74AUP1G74GF |
Low-power D-type flip-flop with set and reset; positive-edge trigger AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| 74HC74DR2 74HC74DG |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
ON Semiconductor
|
